1. Field of the Invention
The present invention relates to a semiconductor device and method of fabricating the same and, more particularly, to a semiconductor device and method of fabricating the same, wherein a contact hole, a via hole and a via contact hole have multiple profiles with various taper angles.
2. Discussion of the Background
Generally, thin film transistors (TFT) are utilized in flat panel displays, image sensors, copiers, printers, scanners, and so forth.
Examples of a flat panel display include a Liquid Crystal Display (LCD), an organic electro-luminescence (EL) device, etc. A representative technology of the flat panel display is the organic EL device, which is may be classified into an active matrix (AM) organic EL device and a passive matrix (PM) organic EL device. An active device such as a TFT controls each pixel in the AM organic EL device. Hence, the AM organic EL device may be superior to the PM organic EL device in terms of speed, viewing angle, and contrast ratio, and it may have a very high resolution.
Silicon TFTs are often used for organic EL devices because they may be fabricated at a low temperature of 400° C. or less, stability of the device characteristics may be excellent, and they may be easily integrated on a large-area glass substrate.
FIG. 1A and FIG. 1B are cross-sectional views showing a conventional method of fabricating a contact hole of a TFT.
FIG. 1A is a cross-sectional view showing a process of forming a buffer layer, a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric on a substrate. As shown in FIG. 1A, a silicon oxide or silicon nitride buffer layer 12 may be formed on an insulating substrate 11 such as plastic or glass, and then an amorphous silicon layer is formed thereon. The amorphous silicon layer may be crystallized to form a polycrystalline silicon layer, which is then patterned to form a semiconductor layer 13. A gate insulating layer 14 may be formed on the entire surface of the substrate, and a material for forming a gate electrode is deposited and patterned to form the gate electrode 15. An interlayer dielectric 16, which protects or insulates elements therebelow and may be made of a silicon oxide layer or a silicon nitride layer, may be formed on the entire surface of the substrate.
FIG. 1B is a cross-sectional view showing a process of forming the contact hole using a photoresist pattern on the substrate. As FIG. 1B shows, a photoresist pattern 17 may be formed and the photoresist is dry etched using the photoresist pattern as a mask to form a contact hole 18. The photoresist pattern 17 is then removed, the contact hole 18 may be filled with a conductive material, and source and drain electrodes (not shown) are formed on the interlayer dielectric 16.
However, in the above-mentioned method of forming the contact hole, as FIG. 2 shows, the dry etching may cause a polymer 21 to be formed below the contact hole 18, which penetrates the interlayer dielectric 17 and the gate insulating layer 14 and exposes a surface of the semiconductor layer 13. Hence, a specific polymer removal solution may be required to remove the polymer 21, which adds an additional process. Further, the surface of the semiconductor layer 13 may be damaged by over etching 22, thereby making contact resistance non-uniform.